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boards: st: stm32h745i_disco: Use PLL2Q as FDCAN clock source #72821
boards: st: stm32h745i_disco: Use PLL2Q as FDCAN clock source #72821
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64 MHz is an odd clock rate for CAN FD. Is it not possible to use one of the CiA recommended clock rates (20, 40, or 80 MHz)?
@henrikbrixandersen It can be done with a small change to the clock tree. Should I change it to 80 MHz? |
When doing so, please check that this won't have impact on other users of the selected domain clock |
I am using CubeMX to validate the clock tree and so far it looks fine, but I will double-check. |
If possible. |
With this configuration of the device tree, we use 80 MHz as a FDCAN bus clock. This configuration allows to pass the tests. Signed-off-by: Tomáš Juřena <jurenatomas@gmail.com>
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Rebased and changed clock to 80 MHz.
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You can probably enable full bitrate testing for this board, then, similar to https://github.com/zephyrproject-rtos/zephyr/blob/main/tests/drivers/can/timing/boards/stm32h735g_disco.conf |
@darkmoon32 Please fix compliance checks |
Enable testing of all CiA recommended bitrates on the STM32H745I. Signed-off-by: Tomáš Juřena <jurenatomas@gmail.com>
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Sure, how about now? |
With this configuration of the device tree, we use 80 MHz as a FDCAN bus clock. This configuration allows to pass the tests.