OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
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Updated
May 28, 2024 - Python
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
An abstraction library for interfacing EDA tools
SystemVerilog to Verilog conversion
A eurorack-friendly audio frontend compatible with many FPGA boards.
FPGA tool performance profiling
XCrypto: a cryptographic ISE for RISC-V
Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe
Plugins for Yosys developed as part of the F4PGA project.
Physical Design Flow from RTL to GDS using Opensource tools.
Examples for the Lushay Labs tang nano 9k series
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