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SCB.ICSR.VECTACTIVE is RES0 on armv8m-baseline w/o halting debug #456

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taralx opened this issue Dec 24, 2022 · 0 comments

taralx commented Dec 24, 2022 •

edited

I know it's a weird combo (no halting debug is rare), but if we read this from IPSR instead of ICSR we avoid the problem altogether.

cortex-m/cortex-m-rt/macros/src/lib.rs

Line 227 in 1a21591

let irqn = unsafe { (core::ptr::read_volatile(SCB_ICSR) & 0x1FF) as i16 - 16 };

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